These synchronous, presettable counters feature an internal carry look-ahead
for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A,
and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163
are 4-bit binary counters. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs change coincident with
each other when so instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting spikes that are normally
associated with asynchronous (ripple clock) counters, however counting spikes
may occur on the (RCO) ripple carry output. A buffered clock input triggers
the four flip-flops on the rising edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be preset
to either level. As presetting is synchronous, setting up a low level at the
load input disables the counter and causes the outputs to agree with the setup
data after the next clock pulse regardless of the levels of the enable inputs.
Low-to-high transitions at the load input of the '160 thru '163 should be
avoided when the clock is low if the enable inputs are high at or before the
transition. This restriction is not applicable to the 'LS160A thru 'LS163A
or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A
is asynchronous and a low level at the clear input sets all four of the flip-flop
outputs low regardless of the levels of clock, load, or enable inputs. The
clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous
and a low level at the clear input sets all four of the flip-flop outputs
low after the next clock pulse, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily as decoding
the maximum count desired can be accomplished with one external NAND gate.
The gate output is connected to the clear input to synchronously clear the
counter to 0000 (LLLL). Low-to-high transitions at the clear input of the
'162 and '163 should be avoided when the clock is low if the enable and load
inputs are high at or before the transition.
The carry look-ahead circuitry provides for cascading counters for n-bit
synchronous applications without additional gating. Instrumental in accomplishing
this function are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be high to count, and input T is fed forward
to enable the ripple carry output. The ripple carry output thus enabled will
produce a high-level output pulse with a duration approximately equal to the
high-level portion of the QA output. This high-level overflow ripple
carry pulse can be used to enable successive cascaded stages. High-to-low
level transitions at the enable P or T inputs of the '160 thru '163 should
occur only when the clock input is high. Transitions at the enable P or T
inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless
of the level of the clock input.
'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock
circuit. Changes at control inputs (enable P or T, or load) that will modify
the operating mode have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting) will be dictated
solely by the conditions meeting the stable setup and hold times.
