The TL16C2550 is a dual universal asynchronous receiver and transmitter (UART). It
incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and
FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate
independently. Another name for the uart function is Asynchronous Communications Element (ACE), and
these terms will be used interchangeably. The bulk of this document describes the behavior of each
ACE, with the understanding that two such devices are incorporated into the TL16C2550.
Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a
functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset
(single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This
relieves the CPU of excessive software overhead by buffering received and to be transmitted
characters. Each receiver and transmitter store up to 16 bytes in their respective FIFOs, with the
receive FIFO including three additional bits per byte for error status. In the FIFO mode, a
selectable autoflow control feature can significantly reduce software overload and increase system
efficiency by automatically controlling serial data flow using handshakes between the
RTS output and CTS input, thus eliminating overruns
in the receive FIFO.
Each ACE performs serial-to-parallel conversions on data received from a peripheral
device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs
parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its
transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes
complete modem control capability and a processor interrupt system that can be tailored to the
application.
Each ACE includes a programmable baud rate generator capable of dividing a reference
clock with divisors from 1 to 65535, thus producing a 16× internal reference clock for the
transmitter and receiver logic. Each ACE accommodates up to a 1.5-Mbaud serial data rate (24-MHz
input clock). As a reference point, that speed would generate a 667-ns bit time and a 6.7-µs
character time (for 8,N,1 serial data), with the internal clock running at 24 MHz.
Each ACE has a TXRDY and RXRDY output that
can be used to interface to a DMA controller.
