The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan
test system. It is suitable for use in embedded IEEE 1149.1 applications and as a component in a
stand-alone boundary scan tester.
The SCANSTA101 is an enhanced version of, and a replacement for, the SCANPSC100. The
SCANSTA101 supports the IEEE 1149.1 Test Access Port (TAP) standard and the IEEE 1532 standard for
in-system configuration of programmable devices.
The SCANSTA101 improves test vector throughput and reduces software overhead in the
system processor. The SCANSTA101 presents a simple, register-based interface to the system
processor. Texas Instruments provides C-language source code which can be included in the embedded
system software. The combination of the SCANSTA101 and its support software comprises a simple API
for boundary scan operations.
The interface from the SCANSTA101 to the system processor is implemented by reading and
writing registers, some of which map to locations in the SCANSTA101 memory. Hardware handshaking
and interrupt lines are provided as part of the processor interface.
The SCANSTA101 is available as a stand-alone device packaged in a 49-pin NFBGA package.
It is also available as an IP macro for synthesis in programmable logic devices.
