TMS320DM814x DaVinci video processors are highly integrated,
programmable platforms that leverage the DaVinci processor technology to meet the processing needs of the following
applications to
name a few: HD Video Conferencing - Skype endpoints
Video Surveillance DVRs IP Netcam Digital
Signage Media Players and Adapters Mobile Medical
Imaging Network Projectors Home Audio and Video
Equipment
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design
Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support,
rich user interfaces, and high processing performance through the maximum flexibility of a fully
integrated mixed processor solution. The device also combines programmable
video and audio processing with a highly
integrated peripheral set.
The TMS320DM814x DaVinci video processors also present OEMs
and ODMs with new levels of processor scalability and software reuse. An OEM or ODM that used the
AM387x processors in a design and can make a similar product with added features could scale up to
the pin-compatible and software-compatible TMS320DM814x processors from TI. The TMS320DM814x
DaVinci video processors add a powerful C674x DSP core along with a video encoder and decoder to
the hardware on the AM38x. Additionally, OEMs or ODMs that have used the AM387x or DM814x
processors and find a need for a faster ARM and DSP core performance could scale up to the
software-compatible AM389x or TMS320DM816x devices
with higher core speeds.
Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP
core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from
A/V algorithms programmed on
the DSP and
coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit
RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data
cache; 512KB of L2 Cache;
48KB of Boot ROM; and
64KB of RAM.
The rich peripheral
set provides the ability to control external peripheral devices and communicate with external
processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides. The peripheral set includes:
HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch]
with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping and Industrial Ethernet ProtocolsTwo
USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant
interfaceTwo 10-serializer McASP audio serial ports (with DIT
mode)Four quad-serilaizer McASP audio serial ports (with DIT
mode)One McBSP multichannel buffered serial portSix UARTs
with IrDA and CIR supportFour SPI serial interfacesThree
MMC/SD/SDIO serial interfacesFour I2C master and
slave interfaces Parallel Camera Interface (CAM)Up to
128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose
timers System watchdog timer Dual DDR2, and DDR3 SDRAM
interfacesFlexible 8- or 16-bit asynchronous memory
interfaceTwo
Controller Area Network (DCAN) modulesSpin LockMailboxSerial
Hard Disk Drive Interface (SATA 300)
The TMS320DM814x DaVinci video processors also include a high-definition video and imaging
coprocessor 2 (HDVICP2), and an SGX530 3D
graphics engine to off-load many video and imaging processing tasks from the DSP core, making more
DSP MIPS available for common video and imaging algorithms. Additionally, it has a complete set of
development tools for both the ARM and DSP, which include C compilers, a DSP assembly optimizer to
simplify programming and scheduling, and a Microsoft® Windows® debugger interface for visibility
into source code execution.
The C674x DSP
core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is
code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation.
The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data
memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable
no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining
memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can
be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip memory accesses
are routed through an MMU.
