This family of 4-, 8-, or 16-differential line receivers (with optional integrated
termination) implements the electrical characteristics of low-voltage differential signaling
(LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard
levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow
operation with a 3-V supply rail.
Any of the differential receivers provides a valid logical output state with a ±100-mV
differential input voltage within the input common-mode voltage range. The input common-mode
voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the
high-speed switching of LVDS signals almost always requires the use of a line impedance matching
resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this
external resistor by integrating it with the receiver.
The intended application of this device and signaling technique is for point-to-point
baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission
media may be printed-circuit board traces, backplanes, or cables. The large number of receivers
integrated into the same substrate along with the low pulse skew of balanced signaling, allows
extremely precise timing alignment of clock and data for synchronous parallel data transfers. When
used with its companion, the 8- or 16-channel driver (the SN65LVDS389 or SN65LVDS387,
respectively), over 200 million data transfers per second in single-edge clocked systems are
possible with little power.
The ultimate rate and distance of data transfer depends on the attenuation
characteristics of the media, the noise coupling to the environment, and other system
characteristics.
