CY54FCT273ATLMB

The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.