These universal, monolithic, nine-bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry and feature odd/even outputs
to facilitate operation of either odd or even parity application. The word-length
capability is easily expanded by cascading as shown under typical application
data.
Series 54LS/74LS and Series 54S/74S parity generators/checkers offer the
designer a trade-off between reduced power consumption and high performance.
These devices can be used to upgrade the performance of most systems utilizing
the '180 parity generator/checker. Although the 'LS280 and 'S280 are implemented
without expander inputs, the corresponding function is provided by the availability
of an input at pin 4 and the absence of any internal connection at pin 3.
This permits the 'LS280 and 'S280 to be substituted for the '180 in existing
designs to produce an identical function even if 'LS280's and 'S280's are
mixed with existing '180's.
These devices are fully compatible with most other TTL circuits. All 'LS280
and 'S280 inputs are buffered to lower the drive requirements to one Series
54LS/74LS or Series 54S/74S standard load, respectively.
