The '166 and 'LS166A 8-bit shift registers are compatible with most other
TTL logic families. All '166 and 'LS166A inputs are buffered to lower the
drive requirements to one Series 54/74 or Series 54LS/74LS standard load,
respectively. Input clamping diodes minimize switching transients and simplify
system design.
These parallel-in or serial-in, serial-out shift registers have a complexity
of 77 equivalent gates on a monolithic chip. They feature gated clock inputs
and an overriding clear input. The parallel-in or serial-in modes are established
by the shift/load input. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with each clock pulse.
When low, the parallel (broadside) data inputs are enabled and synchronous
loading occurs on the next clock pulse. During parallel loading, serial data
flow is inhibited. Clocking is accomplished on the low-to-high-level edge
of the clock pulse through a two-input positive NOR gate permitting one input
to be used as a clock-enable or clock-inhibit function. Holding either of
the clock inputs high inhibits clocking; holding either low enables the other
clock input. This, of course, allows the system clock to be free-running and
the register can be stopped on command with the other clock input. The clock
inhibit input should be changed to the high level only while the clock input
is high. A buffered, direct clear input overrides all other inputs, including
the clock, and sets all flip-flops to zero.
