The SN74HCS164-Q1 device
contains an 8-bit shift register with AND-gated serial inputs and an asynchronous
clear (CLR) input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at either input inhibits entry of the new
data and resets the first flip-flop to the low level at the next clock (CLK) pulse.
A high-level input enables the other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be changed while CLK is high or low,
provided the minimum set-up time requirements are met. Clocking occurs on the
low-to-high-level transition of CLK. All inputs include Schmitt-triggers,
eliminating any erroneous data outputs due to slow-edged or noisy input signals.