SN74AHC74MPWREP

Name: CFS1/2C473J
Brand: KOA Speer Electronics
SKU: 1DD86E-DS
Price: 0.2715 USD
Availability: InStock

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

1 : $0.8519

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Dasenic Part Number

7BD5B1-DS

Manufacturer

Texas Instruments

Manufacturer Part #

SN74AHC74MPWREP

Customer Reference

Datasheet

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Sample

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12355 In Stock

MOQ

1PCS

Delivery Time

Ship Within 48 Hours

Packaging

TSSOP-14

Quantity

Unit Price

$ 0.8519

Total

$ 0.85

* Tax not included , All prices are in USD

Pricing (USD)

Prices are for reference only and aren't final sales prices.

Manufacturer	Texas Instruments
Integrated Circuits (ICs)	Flip Flops
Product Status	Active
Operating Temperature	-55°C ~ 125°C (TA)
Mounting Type	Surface Mount
Package / Case	14-TSSOP (0.173", 4.40mm Width)
Type	D-Type
Output Type	Complementary
Functions	Set(Preset) and Reset
Supplier Device Package	14-TSSOP
Number of Elements	2
Voltage - Supply	2V ~ 5.5V
Clock Frequency	115 MHz
Number of Bits per Element	1
Current - Output High, Low	8mA, 8mA
Max Propagation Delay @ V, Max C L	9.3ns @ 5V, 50pF
Current - Quiescent ( Iq)	2 µA
Trigger Type	Positive Edge
Input Capacitance	2 pF
Series	74AHC
Base Product Number	74AHC74
Packaging	Dasenic-Reel®
Packaging	Cut Tape (CT)
Packaging	Tape & Reel (TR)

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Environmental & Export Classifications

EU RoHS Status	ROHS3 Compliant
MSL Rating	1 (Unlimited, 30°C/85%RH)
REACH Status	REACH Unaffected
US ECCN	EAR99
HTS US	8542.39.0001
China RoHS Status	Green Symbol: Green and environmentally friendly product

Description (v) Features

The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.