The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data
streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that
converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both
receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will
interoperate with a falling edge strobe receiver without any translation logic.
The receiver LVDS clock operates at rates from
20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit
streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock
rate of 85 MHz, each LVDS input line is running at a bit rate of
595 Mbps, resulting in a maximum throughput of
2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366.
The use of these serial link devices is ideal for solving EMI and cable size problems
associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices
are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball
grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin
TSSOP package.
