The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with
the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data
are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3
bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps
per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B
is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe
Receiver (DS90CF366) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide,
high speed TTL interfaces.
