The DS90C383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with
the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data
are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3
bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps
per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B
transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated
pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe
Receiver (DS90CF386) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide,
high speed TTL interfaces.
