The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is
ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25- termination
resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the
CY74FCT573T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the
required setup times are latched when LE transitions from high to low. Data appears on the bus when the
output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode,
data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
