The CDCE62005 is a high performance clock generator and distributor featuring low output
jitter, a high degree of configurability via a SPI interface, and programmable start up modes
determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed
digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz
integration bandwidth).
The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a
clock distribution block including programmable output formats, and an input block featuring an
innovative smart multiplexer. The clock distribution block includes five individually programmable
outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS,
LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew
relationship via a programmable delay block (note that frequency range depends on operational mode
and output format selected). If all outputs are configured in single-ended mode (for example,
LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources
to condition and distribute including any of the three clock inputs or the output of the frequency
synthesizer. The input block includes two universal differential inputs which support frequencies
in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an
external crystal via an on chip oscillator block.
The smart input multiplexer has two modes of operation, manual and automatic. In manual
mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the
input multiplexer will automatically select between the highest priority input clock
available.
